Continued efforts to increase the level of integration for integrated circuits have resulted in smaller feature sizes, more compact devices, and lower power operation. With feature sizes and device profiles becoming smaller, the speed of semiconductor circuitry is becoming less dependent on the switching characteristics of individual devices, e.g., metal oxide semiconductor (MOS) transistors, and more dependant on the resistance and capacitance associated with interconnect. Specifically, it is desirable to provide connections with lower resistance in order to increase current density.
In the past, contacts have been made at the device level by formation of heavily doped regions in the semiconductor material and formation of area-intensive contact windows for connection to metal wire. The size of such windows and the presence of the metal connections consumes area to the exclusion of other wiring on the device level and metal level.
Recent advances in design of the MOS field effect transistor (FET) include the vertical replacement gate transistor. See Hergenrother, et al., “The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length” Technical Digest of the International Electron Devices Meeting, p. 75, 1999. The VRG transistor structure overcomes limitations associated with lithography to achieve a smaller overall transistor geometry. The improvement enables formation of higher density circuit layouts, e.g., SRAM circuits. Nonetheless, it remains desirable to further decrease the area of circuit layouts and reduce limitations on performance such as line resistance.